This invention relates generally to frequency synthesizers and more particularly to a fractional-N frequency synthesizer employing direct digital automatic frequency control useful in radiotelephone communications equipment.
Phase-locked loop (PLL) frequency synthesis is a well known technique for generating one of many related signals from a frequency variable voltage controlled oscillator (VCO). In a single loop PLL, an output signal from the VCO is coupled to a programmable frequency divider which divides by a selected integer number to provide a frequency divided signal to a phase detector. The phase detector compares the frequency divided signal to a reference signal from another fixed frequency oscillator which, often, is selected for stability of frequency over time and environmental changes. Any difference in phase between the frequency divided signal and the reference signal is output from the phase detector, coupled through a loop filter, and applied to the VCO in a manner which causes the output signal from the VCO to change in frequency such that the phase error between the frequency divided signal and the reference signal is minimized. Since the programmable divider divides by integers only, the output frequency step is constrained to be equal to the reference signal frequency.
In order to overcome the limitations of the single loop PLL, programmable frequency dividers capable of effectively dividing by non-integers have been developed. Output frequency step sizes which are fractions of the reference signal frequency are obtained while maintaining a high reference frequency and wide loop bandwidth. Such synthesizers are commonly known as fractional-N synthesizers and a discussion of fractional-N synthesis may be found in U.S. Pat. No. 4,816,774.
The reference signal frequency for the fractional-N frequency synthesizer is, therefore, determined by the step size of the VCO output frequency multiplied by the denominator of the programmable divider divisor. Fractional-N synthesis allows the use of a reference frequency which is much higher than the actual channel spacing and allows designs to use wider bandwidths due to the reduction of low frequency spurious outputs. Wider bandwidths allow fast lock times and the possibility of wideband modulation applied to the reference input or the fractional division scheme.
Control of the divisor of a programmable frequency divider is usually maintained by way of a multiple bit binary number which is applied to the programmable frequency divider. The binary number for a fractional-N synthesizer is created in a digital network and coupled to the programmable frequency divider. Description of divider controls may be found in U.S. patent application Ser. No. 516,897, (now U.S. Pat. No. 5,055,800) "Fractional N/M Synthesis", filed in behalf of Black et al. on Apr. 30, 1990; U.S. patent application Ser. No. 576,333, "Latched Accumulator Fractional-N Synthesis with Residual Error Reduction", filed in behalf of Hietala et al. on Aug. 31, 1990; and U.S. patent application Ser. No. 576,342, (now U.S. Pat. No. 5,070,310) "Multiple Latched Accumulator Fractional-N Synthesis", filed in behalf of Hietala et al. on Aug. 31, 1990.
Modulation of a fractional-N synthesizer has been accomplished by adding or subtracting a digital value, corresponding to the modulation signal, from the digital number applied to the programmable divider which establishes the divisor value. One such technique of modulation has been described in U.S. patent application Ser. No. 516,993, (now U.S. Pat. No. 5,055,802) "Multiaccumulator Sigma-Delta Fractional-N Synthesis", filed in behalf of Hietala et al. on Apr. 30, 1991. There, modulation is coupled to a fractional-N synthesizer as the sixteen least significant bits of a twenty-four bit channel control number.
Automatic Frequency Control (AFC) of radio equipment is typically achieved by automatically causing fine corrections to the frequency of a reference oscillator based upon a higher stability standard. One example of an AFC derived from an external standard is described in U.S. Pat. No. 4,887,050 in which a frequency offset between a received signal and a digital receiver local oscillator is corrected in substantially one step.
Such AFC networks for digital receivers, however, require a conversion from the digital detection accomplished by the digital receiver to an analog correction signal to be applied to the local oscillator. The conversion requires additional components. Thus, it would be advantageous to realize a digital synthesizer in which the AFC could be combined with the modulation and the digital to analog AFC conversion could be eliminated.